This application is related to Japanese application No. Hei 12(2000)-113784 filed on Apr. 14, 2000, whose priority is claimed under 35 USC xc2xa7119, the disclosure of which is incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a structure of an interlayer insulation film for use in a semiconductor device having a miniature structure based on a design rule of a submicron order, and a method for fabricating the interlayer insulation film.
2. Description of Related Art
As semiconductor devices are becoming more and more highly integrated, there is an increasing demand for multi-layer interconnection. In formation of the multi-level interconnection, it is necessary to smoothly flatten an interlayer insulation film provided between two wiring layers in order that steps in a first wiring layer do not cause a break in a second wiring layer. To flatten the interlayer insulation film, there has been widely used a silicon oxide film formed by a coating and sintering method. The silicon oxide film thus formed involves the problem of generation of particles or cracks or the problem of diffusion of water contained in the film, which leads to deterioration of characteristics of transistors of a semiconductor device.
In recent years, a silicon oxide film (referred to as TEOS/O3xe2x80x94SiO2 film hereinafter) formed by an atmospheric CVD process using tetraethylorthosilicate (referred to as TEOS hereinafter) and ozone as materials is receiving attention as the interlayer insulation film and is becoming in practical use. The TEOS/O3xe2x80x94SiO2 film is advantageous in that it can be formed at a low temperature of 400xc2x0 C. or lower and that it covers steps in a flow form already at its deposition.
However, the deposition rate of the TEOS/O3xe2x80x94SiO2 film is strongly dependent on an under layer, and tends to vary depending on a material and a configuration of the under layer. For example, the deposition rate of the TEOS/O3xe2x80x94SiO2 film is high when the film is deposited on a silicon substrate while the deposition rate is low when the film is deposited on an insulation film such as a SiO2 film.
Further, the TEOS/O3xe2x80x94SiO2 film has a high content of water therein. Therefore, in the cases where the film was used as an interlayer insulation film for covering a MOS device, water in the film diffuses into the MOS device. As a result, hot carriers are generated at operation of the MOS device, and reduce the reliability of the device.
To solve this problem, there have been conceived various methods as disclosed, for example, in Japanese Unexamined Patent Publication Nos. Hei 5(1993)-41459 and Hei 7(1995)-335753. In these methods, a thin silicon nitride film is formed on a first wiring layer, and the TEOS/O3xe2x80x94SiO2 film is deposited thereon. Thus, the silicon nitride film is formed prior to the deposition of the TEOS/O3xe2x80x94SiO2 film, so that the dependence of the deposition rate of the TEOS/O3xe2x80x94SiO2 film on the under layer is controlled and water is blocked off, thereby ensuring reliability.
The above-mentioned methods can control the dependence of the deposition rate of the TEOS/O3xe2x80x94SiO2 film on the under layer. In the cases where the first wiring film is thick, however, water in the TEOS/O3xe2x80x94SiO2 film cannot be sufficiently blocked off, which sometimes reduced the reliability of the MOS device.
This inability of the TEOS/O3xe2x80x94SiO2 film to block off water is due to the fact that the silicon nitride film is too thin (20 nm in an example of Japanese Unexamined Patent Publication No. Hei 5(1991)-41459) to completely cover sidewalls (portions A in FIG. 2(a)) of the thick first wiring film. In FIGS. 2(a) and 2(b), numerals 1, 2 and 3 designate the first wiring film, the silicon nitride film and the TEOS/O3xe2x80x94SiO2 film, respectively.
To deal with the above situation, it is conceived to thicken the silicon nitride film (for example, around 100 nm or more) to completely cover the sidewalls. When the silicon nitride film is made thick, however, there arises a problem that the silicon nitride film comes off the first wiring layer or cracks occur in the silicon nitride film itself due to a stress within the film.
The object of the present invention is to control the dependence of the deposition rate of the TEOS/O3xe2x80x94SiO2 film on the under layer and prevent water contained in the TEOS/O3xe2x80x94SiO2 film from diffusing into the MOS device, thereby ensuring the high reliability of the MOS device.
Thus, the present invention provides a semiconductor device comprising: a first wiring layer formed on a semiconductor substrate with an insulation film interposed therebetween, an interlayer insulation film and a second wiring layer formed on the first wiring layer in this order, wherein the interlayer insulation film is composed, from a first wiring layer side, of a first silicon oxide film having a compressive stress within the film, a silicon nitride film having a compressive stress within the film, a second silicon oxide film having a tensile stress within the film, and a third silicon oxide film having a compressive stress within the film.
Further, the present invention a method for manufacturing a semiconductor device comprising the steps of: forming a first wiring layer on a semiconductor substrate with an insulation film interposed therebetween, forming on the first wiring layer a first silicon oxide film having a compressive stress within the film and a silicon nitride film having a compressive stress within the film in this order, forming on the silicon nitride film a second silicon oxide film having a tensile stress within the film, forming on the second silicon oxide film a third silicon oxide film having a compressive stress within the film, and forming a second wiring layer on the third silicon oxide film.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.